Diode Dynamics for Redundant OR‑ing & ESD

Redundant power feeds keep servers alive when a supply dies, but the wrong OR‑ing strategy burns precious thermal headroom and invites field risk. At the same time, ESD and surge events at the chassis entry can slip past poor clamps and wreak havoc on high‑speed links and power rails. If your team also needs clean, audit‑ready evidence for IEC tests, the bar gets higher.

This guide distills what works on production server and storage boards: how to pick and place ideal‑diode controllers versus Schottky diodes for redundant OR‑ing, how to stage ESD and surge suppression near power and high‑speed ingress without breaking SI, and how to assemble a compliance matrix that passes procurement scrutiny. Along the way, you’ll see quick math, layout rules that matter, and the exact artifacts auditors expect.

Active vs passive OR‑ing for redundant PSUs on 12 V and 48 V

Schottky OR‑ing is simple, but the forward drop scales painfully at current. MOSFET‑based ideal‑diode controllers sense polarity and drive one or more FETs so the path looks like a milliohm‑class resistor, with fast reverse‑current blocking. Texas Instruments’ engineering note shows measured drops for MOSFET ideal diodes that are an order of magnitude below Schottky at 10 A and explains the control behavior and layout considerations in depth; see the Basics of Ideal Diodes application report for the quantitative backdrop and examples in 2025‑era devices. According to the discussion in the report, a typical Schottky around 10 A drops roughly half a volt while an ideal‑diode MOSFET path can be tens of millivolts, dramatically reducing loss and heat.

A quick conduction‑loss comparison

Calculated example assuming:

Schottky forward drop Vf ≈ 0.5 V at the operating current and temperature (representative value; use your datasheet curve).

Ideal‑diode path made from paralleled MOSFETs yielding RDS(on)(hot) ≈ 1.5 mΩ (representative for multi‑FET stages). Power P ≈ I²·R.

These assumptions are conservative but realistic for server OR‑ing with decent copper and airflow. Replace with your chosen device parameters during design reviews.

Within the current range of 10A to 100A, the Schottky voltage drop is constant at 0.50V and the power increases with current, while the voltage drop (I·R) and power of an ideal diode both increase with current, and both values are much lower than the corresponding voltage drop and power of the Schottky diode.

What changes at 48 V? The rail voltage doesn’t change conduction loss directly, but it does change fault energy and MOSFET stress. Favor controllers and FETs with adequate VDS margin (often 60–100 V for 48 V distribution) and check SOA against load steps and surge transients. Devices like LM74700‑class controllers implement fast reverse blocking; back‑to‑back FET architectures from ADI and TI stop reverse conduction even under supply asymmetry.

Layout and thermal notes that move the needle

Keep the OR‑ing current path short and wide. Use thick copper pours, generous via stitching under the FETs, and symmetric splits when paralleling.

Use Kelvin source sensing when the controller recommends it to prevent error from IR drop in high current paths.

Minimize gate loop inductance; route the sense and gate lines away from noisy power loops.

Validate RDS(on) at temperature. Model or measure with the intended airflow; record assumptions in the design dossier so reviews don’t debate invisible margins.

Surge and ESD suppression at power and high‑speed ingress

Effective suppression is a game of placement, return path, and appropriate device selection for both power rails and multi‑gigabit links.

Place the primary clamp at the connector. Strive for the shortest possible connection between the protected line and the TVS, and between the TVS and a low‑impedance return. It’s about cutting loop inductance, not hitting a magic millimeter number.

Power rails at 12 V and 48 V need correctly rated VR, VC, and IPP. A practical method is to pick VR ≥ worst‑case steady line, verify VC at the standard surge profile stays below downstream tolerance, and ensure IPP exceeds the anticipated surge current.

Don’t forget chassis strategy. Decide early where shields land to chassis and what your DC and RF return paths look like. This decision sets your clamp effectiveness and how the surge energy flows.

For test planning and expected threat profiles at the system level, refer to IEC waveforms and level definitions. A concise overview for surge (combination wave 1.2/50 µs and 8/20 µs) lives here: Ametek CTS overview of IEC 61000‑4‑5 surge.

Diode dynamics redundant OR‑ing ESD surge protection server PCB in a worked example

Let’s quantify what the OR‑ing choice costs in heat, then sanity‑check a suppression placement.

Example 1 — 12 V rail at 60 A:

Schottky OR‑ing using a device with ≈0.5 V forward drop dissipates roughly 30 W per path. In a dual‑feed system, that’s a thermal liability during steady load sharing and a reliability hit during a failover surge.

Ideal‑diode controller with paralleled MOSFETs totaling ≈1.5 mΩ hot: P ≈ I²·R = 60²·0.0015 ≈ 5.4 W. The drop is ≈90 mV, which also preserves regulation headroom for downstream VRMs.

Example 2 — 48 V rail at 60 A:

Schottky: same 30 W lost as heat for the conduction path; thermal rise is worse because 48 V systems often sit in tighter power bays and see higher fault energy during transients.

Ideal‑diode: ≈5.4 W with the same FET assumptions. Check FET SOA at 48 V for line steps and ensure the controller’s reverse‑blocking time is in the microsecond class.

Now sanity‑check ingress suppression for the 12 V rail:

Choose VR ≥ the worst‑case line (for example, 16 V to clear tolerance and transient headroom) and confirm VC at the 8/20 µs surge keeps the downstream OR‑ing path below its absolute max. Place the TVS immediately at the connector with a short, direct return to chassis or power‑ground reference.

Closing and practical next steps

If you’re deciding between Schottky and ideal‑diode controllers for redundant feeds, run the conduction math with hot RDS(on), check SOA at your surge levels, and lock down ingress TVS placement before routing. For compliance, build your matrix up front, name every evidence artifact you’ll capture, and make it repeatable.